Haven't had much luck with this on the microchip forums.
I currently have a PIC32MZ1024EFE100 micro and am using the DMA/PMP for a controllerless graphics display, 320x240 16-bit.
I am having some problems with an intermittant flickering which I think I have tracked down to accessing the frameBuffer while the DMA is transferring data from it. When I only write to the buffer in the vertical porch (DMA using a dummy buffer to send 10 lines of dummy data) the flickering doesn't seem to happen.
My frame buffer is coherent so there shouldn't be a problem of cached data but when I check the K0 bits in the Config CPU register, it always reads 0 which is the' Cacheable, non-coherent, write-through, no write allocate' cache policy but the default according to multiple data sheets and app-notes should be 3 'Cacheable, non-coherent, write-back, write allocate'
I am not using Harmony as I never got on with it and this design was originally for a PIC32MX so I ported the code ok to the MZ but have this flickering issue.
The startup code should set the cache policy I thought, and any attempt I make at trying to write to K0 fails. I can't seem to get the harmony sys_devcon macros to work so have tried this:
- Code: Select all
#define UNCACHED 0x02
#define WB_WA 0x03
#define WT_WA 0x01
#define WT_NWA 0x00
void SetCachePolicy(int cc)
{
unsigned int cpO;
cpO = _mfc0(16, 0);
cpO &= ~0x03;
cpO |= cc;
_mtc0(16, 0,cpO);
}
Can anyone help? Cheers!