Why is the duty cycle much wider than it should be? PIC32MZ

Why is the duty cycle much wider than it should be? PIC32MZ

Postby DominusRRR » Tue Oct 27, 2020 10:32 pm

Hi.

I'm working with the PIC32MZ2048EFM100 and XC32.

I'm using some outputs as PWM signal generators.

There are frequencies for which the pwm works fine, but not for others.

For example to get 24.4 kHz, I make the following configurations:

PR2 = 255 (I use timer 2)

TCKPS<2:0> = 011 = 1:8 prescale value

TPB = 1/50 MHz

Duty Cycle = OC1RS = 0x05.

If the period is given by PR2 plus 1, which would be 256, the duty cycle is very small, but when analyzing this signal with an oscilloscope, the duty cycle is very long, greater than 50% of the signal period.

Any suggestion of what's up?


I attach an image of the signal displayed on the oscilloscope and a capture of the registers T2CON, OC1RS and PR2.
Attachments
osc.jpg
oscilloscope
osc.jpg (198.59 KiB) Viewed 248 times
SFR.png
T2CON, OC1RS & PR2
SFR.png (6.15 KiB) Viewed 248 times
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Re: Why is the duty cycle much wider than it should be? PIC3

Postby DominusRRR » Tue Oct 27, 2020 11:34 pm

I forgot to add the value of OC1CON. It is 0xC006
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Re: Why is the duty cycle much wider than it should be? PIC3

Postby ric » Wed Oct 28, 2020 11:59 pm

Are you sure it's using TMR2?
How is the OCACLK bit in CFGCON set?
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Re: Why is the duty cycle much wider than it should be? PIC3

Postby DominusRRR » Thu Oct 29, 2020 4:06 pm

ric wrote:Are you sure it's using TMR2?
How is the OCACLK bit in CFGCON set?



Hi. Thanks for write.

We have discovered the problem.

We verified that in the hardware that was prototype that works without problems, after careful review, it was discovered that the problem was the optocoupler that drives the CMOS transistor.

Although it is high frequency, it doesn't work as indicated by the manufacturer.

It seems that we received a batch with some problem, but it seems that it is a counterfeit of the original chip, since we did not buy them from a recognized supplier.
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