Has Interrupt-On-Change "Changed" in Enhanced Core?

Enhanced mid-range devices. PIC12F1xxx and PIC16F1xxx

Has Interrupt-On-Change "Changed" in Enhanced Core?

Postby tunelabguy » Sat Jan 17, 2015 11:24 pm

A long time ago I developed some PIC code using Interrupt-On-Change. At that time and for that particular PIC (it was a 14-bit core), it was necessary to read the I/O port to clear the mismatch condition to clear the interrupt. Now I am again developing some code using Interrupt-On-Change, this time for a 16F1783, enhanced core. In reading the section in the manual about Interrupt-On-Change, there is no longer any mention of "reading the port to clear the mismatch condition". Instead it looks like there are now some new registers (IOCxF) with individual interrupt flags for each port bit, and these flags are supposed to be cleared in software to clear an interrupt. Reading the port explicitly no longer plays a role in clearing the interrupt. (It is also neat that now we have access to separate enabling of rising and falling edges.)

Does anyone know the history of this evolution, and without looking at each and every datasheet, which PICs this new method applies to? I am curious about the reasoning behind the change.
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Re: Has Interrupt-On-Change "Changed" in Enhanced Core?

Postby DavidEGrayson » Fri Jan 23, 2015 7:46 pm

Hmm, the Interrupt-on-change (a.k.a. port chage) features of the PIC18F14K50, PIC18F4550, and PIC18F25K50/45K50 all require you to read a port in order to clear a mismatch condition. The PIC10F322 doesn't require it.

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Re: Has Interrupt-On-Change "Changed" in Enhanced Core?

Postby jtemples » Wed Feb 11, 2015 10:10 pm

IOC on the enhanced core is new from scratch, having nothing in common with the older PIC16/PIC18 implementation other than the name. In addition to being more flexible, it fixes the bug that the older parts have that could cause IOC interrupts to be lost when reading the port.

Hopefully this implementation will show up on newer PIC18 parts.
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