Issues with RTCC Code Generated by MCC

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Issues with RTCC Code Generated by MCC

Postby MBElectronicDesign » Sun Aug 07, 2016 1:23 pm

I created a project that uses a 2x16 LCD display and a PIC24FJ128GA202 - it's intended as a building block project for anything that needs a real-time clock and a simple user interface. There is a 32.768 kHz crystal as the SOSC and the chip runs off it's internal oscillator at 8 MHz. Although it's the first prototype and the code is at a very early stage, I have a reliable LCD driver that I developed from various examples.
I got code running by using the MPLAB Code Configurator (MCC) from within MPLAB X. It all compiles with zero errors but the seconds never increment from the original time that's set in the initialization routine; I've proved the secondary oscillator is running by scoping the crystal. The MCC generated initialization code is...
Code: Select all
// CONFIG4
#pragma config DSWDTPS = DSWDTPS1F    // Deep Sleep Watchdog Timer Postscale Select bits->1:68719476736 (25.7 Days)
#pragma config DSWDTOSC = LPRC    // DSWDT Reference Clock Select->DSWDT uses LPRC as reference clock
#pragma config DSBOREN = ON    // Deep Sleep BOR Enable bit->DSBOR Enabled
#pragma config DSWDTEN = ON    // Deep Sleep Watchdog Timer Enable->DSWDT Enabled
#pragma config DSSWEN = ON    // DSEN Bit Enable->Deep Sleep is controlled by the register bit DSEN
#pragma config PLLDIV = DISABLED    // USB 96 MHz PLL Prescaler Select bits->PLL Disabled
#pragma config I2C1SEL = DISABLE    // Alternate I2C1 enable bit->I2C1 uses SCL1 and SDA1 pins
#pragma config IOL1WAY = ON    // PPS IOLOCK Set Only Once Enable bit->Once set, the IOLOCK bit cannot be cleared

// CONFIG3
#pragma config WPFP = WPFP127    // Write Protection Flash Page Segment Boundary->Page 127 (0x1FC00)
#pragma config SOSCSEL = ON    // SOSC Selection bits->SOSC circuit selected
#pragma config WDTWIN = PS25_0    // Window Mode Watchdog Timer Window Width Select->Watch Dog Timer Window Width is 25 percent
#pragma config PLLSS = PLL_PRI    // PLL Secondary Selection Configuration bit->PLL is fed by the Primary oscillator
#pragma config BOREN = ON    // Brown-out Reset Enable->Brown-out Reset Enable
#pragma config WPDIS = WPDIS    // Segment Write Protection Disable->Disabled
#pragma config WPCFG = WPCFGDIS    // Write Protect Configuration Page Select->Disabled
#pragma config WPEND = WPENDMEM    // Segment Write Protection End Page Select->Write Protect from WPFP to the last page of memory

// CONFIG2
#pragma config POSCMD = NONE    // Primary Oscillator Select->Primary Oscillator Disabled
#pragma config WDTCLK = SOSC    // WDT Clock Source Select bits->WDT uses SOSC input
#pragma config OSCIOFCN = ON    // OSCO Pin Configuration->OSCO/CLKO/RA3 functions as port I/O (RA3)
#pragma config FCKSM = CSECME    // Clock Switching and Fail-Safe Clock Monitor Configuration bits->Clock switching is enabled, Fail-Safe Clock Monitor is enabled
#pragma config FNOSC = FRCDIV    // Initial Oscillator Select->Fast RC Oscillator with Postscaler (FRCDIV)
#pragma config ALTCMPI = CxINC_RB    // Alternate Comparator Input bit->C1INC is on RB13, C2INC is on RB9 and C3INC is on RA0
#pragma config WDTCMX = LPRC    // WDT Clock Source Select bits->WDT always uses LPRC as its clock source
#pragma config IESO = ON    // Internal External Switchover->Enabled

// CONFIG1
#pragma config WDTPS = PS32768    // Watchdog Timer Postscaler Select->1:32768
#pragma config FWPSA = PR128    // WDT Prescaler Ratio Select->1:128
#pragma config WINDIS = OFF    // Windowed WDT Disable->Standard Watchdog Timer
#pragma config FWDTEN = OFF    // Watchdog Timer Enable->WDT disabled in hardware; SWDTEN bit disabled
#pragma config ICS = PGx1    // Emulator Pin Placement Select bits->Emulator functions are shared with PGEC1/PGED1
#pragma config LPCFG = OFF    // Low power regulator control->Disabled - regardless of RETEN
#pragma config GWRP = OFF    // General Segment Write Protect->Write to program memory allowed
#pragma config GCP = OFF    // General Segment Code Protect->Code protection is disabled
#pragma config JTAGEN = OFF    // JTAG Port Enable->Disabled

#include "mcc.h"

void SYSTEM_Initialize(void)
{
    PIN_MANAGER_Initialize();
    INTERRUPT_Initialize();
    OSCILLATOR_Initialize();
    ADC1_Initialize();
    OC1_Initialize();
    TMR2_Initialize();
    RTCC_Initialize();
    TMR1_Initialize();
}

void OSCILLATOR_Initialize(void)
{
    // CF no clock failure; NOSC FRCDIV; SOSCEN enabled; POSCEN disabled; CLKLOCK unlocked; OSWEN Switch is Complete; IOLOCK not-active;
    __builtin_write_OSCCONL((uint8_t) (0x0702 & 0x00FF));
    // PLLEN disabled; RCDIV FRC/1; DOZE 1:8; DOZEN disabled; ROI disabled;
    CLKDIV = 0x3000;
    // STOR disabled; STORPOL Interrupt when STOR is 1; STSIDL disabled; STLPOL Interrupt when STLOCK is 1; STLOCK disabled; STSRC SOSC; STEN enabled; TUN Center frequency;
    OSCTUN = 0x8000;
    // ROEN disabled; ROSEL FOSC; ROSIDL disabled; ROSWEN disabled; ROOUT disabled; ROSLP disabled;
    REFOCONL = 0x0000;
    // RODIV 0;
    REFOCONH = 0x0000;
    // ROTRIM 0;
    REFOTRIML = 0x0000;
    // WDTO disabled; TRAPR disabled; SLEEP disabled; BOR disabled; DPSLP disabled; CM disabled; SWR disabled; SWDTEN disabled; EXTR disabled; POR disabled; IDLE disabled; IOPUWR disabled; VREGS disabled;
    RCON = 0x0000;
}

and the RTCC initialization routine is...
Code: Select all
void RTCC_Initialize(void)
{

   // Set the RTCWREN bit
   __builtin_write_RTCWEN();

   RCFGCALbits.RTCEN = 0;
   
   if(!RTCCTimeInitialized())
   {
       // set RTCC time 2016-06-30 08-05-28
       RCFGCALbits.RTCPTR = 3;        // start the sequence
       RTCVAL = 0x16;    // YEAR
       RTCVAL = 0x630;    // MONTH-1/DAY-1
       RTCVAL = 0x408;    // WEEKDAY/HOURS
       RTCVAL = 0x528;    // MINUTES/SECONDS
   }

   // RTCOUT Alarm Pulse; PWSPRE disabled; RTCLK SOSC; PWCPRE disabled; PWCEN disabled; PWCPOL disabled;
   RTCPWC = 0x0000;

           
   // Enable RTCC, clear RTCWREN
   RCFGCALbits.RTCEN = 1;
   RCFGCALbits.RTCWREN = 0;

   //Enable RTCC interrupt
   IEC3bits.RTCIE = 1;
}

I tried to post this on the main Microchip forum for MCC but was unable to post the actual code due to Access Denied' errors that seem to have been around for years! Anyway, rodims on that forum told me that he had a similar issue that was due to the MCC not generating the correct code to set up the RTCC. In my code above, the RTCPWC = 0x000 statement is suspicious because the RTCC document that's offered by the main page for the PIC24FJ128GA202 links to document DS39696B but the RTCPWC register does not appear in the DS39696B document at all; something is very wrong with the MCC-generated configuration.

Any ideas?
MBElectronicDesign
 
Posts: 1
Joined: Sun Aug 07, 2016 12:01 pm
PIC experience: Professional 5+ years with MCHP products

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