PIC18F27k42 CLKOUT NOT WORKING
Posted: Fri Jun 08, 2018 7:09 pm
Hello all, this is my first post here.
I have designed and built a board that includes a PIC18LF27K42 MCU.
I am using the Microchip MPLAB X IDE v 4.15.
I want the MCU to run on one of its internal oscillators and am trying to get it to run specifically at 7.75KHz (31KHz / 4). I wrote a routine that simply toggles a couple of bits on PORT A just to make sure that the MPU is alive. It is.
I can tell that the MCU is running pretty slowly because the bits are toggling very slowly. However, I need to know what the system clock speed actually is. My problem is that I cannot get the CLKOUT signal to appear on the RA6 bit (pin 7 on my 28-pin QFN).
According to the part's data sheet on page 67:
Register 5-2: Configuration Word 1H (300001h)
“bit 0 /CLKOUTEN: Clock Out Enable bit
If FEXTOSC<2:0> = EC (high, mid or low) or Not Enabled:
1 = CLKOUT function is disabled; I/O or oscillator function on OSC2
0 = CLKOUT function is enabled; Fosc/4 clock appears at OSC2
Otherwise:
This bit is ignored.”
I have of course set the /CLKOUTEN bit to ZERO and I set FEXTOSC<2:0> to "NOT ENABLED".
So my question is: Can the CLKOUT bit be enabled when using the 32KHz internal oscillator? According to what I quoted above the answer would seem to be YES. So if that is indeed the case, what am I missing?
I have pasted my configuration file and my test main() file below. I will appreciate any help I can get.
Thanks,
Ray Russell
Houston, TX
I have designed and built a board that includes a PIC18LF27K42 MCU.
I am using the Microchip MPLAB X IDE v 4.15.
I want the MCU to run on one of its internal oscillators and am trying to get it to run specifically at 7.75KHz (31KHz / 4). I wrote a routine that simply toggles a couple of bits on PORT A just to make sure that the MPU is alive. It is.
I can tell that the MCU is running pretty slowly because the bits are toggling very slowly. However, I need to know what the system clock speed actually is. My problem is that I cannot get the CLKOUT signal to appear on the RA6 bit (pin 7 on my 28-pin QFN).
According to the part's data sheet on page 67:
Register 5-2: Configuration Word 1H (300001h)
“bit 0 /CLKOUTEN: Clock Out Enable bit
If FEXTOSC<2:0> = EC (high, mid or low) or Not Enabled:
1 = CLKOUT function is disabled; I/O or oscillator function on OSC2
0 = CLKOUT function is enabled; Fosc/4 clock appears at OSC2
Otherwise:
This bit is ignored.”
I have of course set the /CLKOUTEN bit to ZERO and I set FEXTOSC<2:0> to "NOT ENABLED".
So my question is: Can the CLKOUT bit be enabled when using the 32KHz internal oscillator? According to what I quoted above the answer would seem to be YES. So if that is indeed the case, what am I missing?
I have pasted my configuration file and my test main() file below. I will appreciate any help I can get.
Thanks,
Ray Russell
Houston, TX
- Code: Select all
**************************** configuration data ******************************
// PIC18LF27K42 Configuration Bit Settings
// 'C' source line config statements
// CONFIG1L
#pragma config FEXTOSC = OFF // External Oscillator Selection (Oscillator not enabled)
#pragma config RSTOSC = HFINTOSC_1MHZ// Reset Oscillator Selection (HFINTOSC with HFFRQ = 4 MHz and CDIV = 4:1)
// CONFIG1H
#pragma config CLKOUTEN = ON // Clock out Enable bit (CLKOUT function is enabled)
#pragma config PR1WAY = OFF // PRLOCKED One-Way Set Enable bit (PRLOCK bit can be set and cleared repeatedly)
#pragma config CSWEN = ON // Clock Switch Enable bit (Writing to NOSC and NDIV is allowed)
#pragma config FCMEN = OFF // Fail-Safe Clock Monitor Enable bit (Fail-Safe Clock Monitor disabled)
// CONFIG2L
#pragma config MCLRE = EXTMCLR // MCLR Enable bit (If LVP = 0, MCLR pin is MCLR; If LVP = 1, RE3 pin function is MCLR )
#pragma config PWRTS = PWRT_OFF // Power-up timer selection bits (PWRT is disabled)
#pragma config MVECEN = ON // Multi-vector enable bit (Multi-vector enabled, Vector table used for interrupts)
#pragma config IVT1WAY = OFF // IVTLOCK bit One-way set enable bit (IVTLOCK bit can be cleared and set repeatedly)
#pragma config LPBOREN = OFF // Low Power BOR Enable bit (ULPBOR disabled)
#pragma config BOREN = OFF // Brown-out Reset Enable bits (Brown-out Reset disabled)
// CONFIG2H
#pragma config BORV = VBOR_2P85 // Brown-out Reset Voltage Selection bits (Brown-out Reset Voltage (VBOR) set to 2.8V)
#pragma config ZCD = OFF // ZCD Disable bit (ZCD disabled. ZCD can be enabled by setting the ZCDSEN bit of ZCDCON)
#pragma config PPS1WAY = OFF // PPSLOCK bit One-Way Set Enable bit (PPSLOCK bit can be set and cleared repeatedly (subject to the unlock sequence))
#pragma config STVREN = ON // Stack Full/Underflow Reset Enable bit (Stack full/underflow will cause Reset)
#pragma config DEBUG = ON // Debugger Enable bit (Background debugger enabled)
#pragma config XINST = ON // Extended Instruction Set Enable bit (Extended Instruction Set and Indexed Addressing Mode enabled)
// CONFIG3L
#pragma config WDTCPS = WDTCPS_0// WDT Period selection bits (Divider ratio 1:32)
#pragma config WDTE = OFF // WDT operating mode (WDT Disabled; SWDTEN is ignored)
// CONFIG3H
#pragma config WDTCWS = WDTCWS_3// WDT Window Select bits (window delay = 50 percent of time; no software control; keyed access required)
#pragma config WDTCCS = LFINTOSC// WDT input clock selector (WDT reference clock is the 31.0 kHz LFINTOSC)
// CONFIG4L
#pragma config BBSIZE = BBSIZE_8192// Boot Block Size selection bits (Boot Block size is 8192 words)
#pragma config BBEN = ON // Boot Block enable bit (Boot block enabled)
#pragma config SAFEN = ON // Storage Area Flash enable bit (SAF enabled)
#pragma config WRTAPP = OFF // Application Block write protection bit (Application Block not write protected)
// CONFIG4H
#pragma config WRTB = OFF // Configuration Register Write Protection bit (Configuration registers (300000-30000Bh) not write-protected)
#pragma config WRTC = OFF // Boot Block Write Protection bit (Boot Block (000000-0007FFh) not write-protected)
#pragma config WRTD = OFF // Data EEPROM Write Protection bit (Data EEPROM not write-protected)
#pragma config WRTSAF = OFF // SAF Write protection bit (SAF not Write Protected)
#pragma config LVP = ON // Low Voltage Programming Enable bit (Low voltage programming enabled. MCLR/VPP pin function is MCLR. MCLRE configuration bit is ignored)
// CONFIG5L
#pragma config CP = OFF // PFM and Data EEPROM Code Protection bit (PFM and Data EEPROM code protection disabled)
// CONFIG5H
// #pragma config statements should precede project file includes.
// Use project enums instead of #define for ON and OFF.
#include <xc.h>
******************************* End of configuration header file *****************************
****************************** main() file **********************************
OSCCON1 = 0xd7; // 0xd2 = NEW OSC TYPE & DIV RATIO: LFINTOSC & DIVIDE BY 4
OSCCON3 = 0x80; // NOT RELEVANT
OSCFRQ = 0xf0; // 0xf0 = 1MHZ WHICH IS THE LOWEST POSSIBLE HFINTOSC (ONLY) FREQUENCY
OSCTUNE = 0xc0; // 0xc0 = TUNED TO HFINTOSC (ONLY) CENTER FREQUENCY
OSCEN = 0x10; // 0x10 = LFINTOSC (ONLY) EXPLICTLY ENABLED
//*************************************************
// REFERENCE CLOCK PARAMETERS
CLKRCON = 0x97; // 0x97 = rclk enabled, 50% duty cycle, div by 128
CLKRCLK = 0xf2; // 0xf1 = HFINTOSC; 0xf2 = LFINTOSC; 0xf3 = MFINTOSC
//******************************************************************
// Note: port directions : 1=input, 0=output
TRISA = 0x82; /* this sets the port A pins to outputs except for bit 7 (clkin) and bit 1 (SDI) */
TRISB = 0x00; /* this sets the port B pins to outputs */
TRISC = 0x00; /* this sets the port C pins to outputs */
LATA = 0; /* this writes zeros into all of the port A latches */
LATB = 0; /* this writes zeros into all of the port B latches */
LATC = 0; /* this writes zeros into all of the port C latches */
RC0PPS = 0x27; /* hopefully map clkrout to port C(7), which should be MCU pin 8 */
/******************** beginning of bit toggle code **********************/
while(1)
{
PORTA = 0b000110000; // Set RA4 and RA5
for(i=0; i<167; i++);
PORTA = 0b00000000; // Clear RA4 and RA5
for(i=0; i<167; i++);
}
}