SSP in Master Mode (Interrupt Problems)

(instructions, reset, WDT, specifications...) PIC17Cxx, PIC18Fxxx

SSP in Master Mode (Interrupt Problems)

Postby SLTom992 » Mon Jun 23, 2014 6:13 pm

I'm having a problem with interrupts that is stumping me. (PIC18F45K22)

I have a timer interrupt in which I set a flag.
Additionally in the isp I have an SSP1STAT call on Buffer Full.

The idea is that I am operating the SSP in Master Mode to read a 32 bit word using the 8 bit Serial Input Register. I am reading the SDI then or'ing it with a LONG variable. I then left shift the LONG to make room for the new SPI input.

Between Buffer Full interrupts I am returning to the program. So each pass is only once per buffer full.

Code: Select all
char measure;
long measure1;
long instant_read;

void interrupt myIsr (void){

    // test for timer timeout (250 usec on a 4 MHz external clock)
    if (TMR3IF) {                               // If timer int. kick counter
        if (timer3_int)
            timer3_int--;                       // decriment counter
        TMR3H = 0xFF;
        TMR3L = 0x41;
        TMR3IF = FALSE;                     // clear for next timer int
        TMR3IE = TRUE;                      // Reenable interrupt
    }
    // Test for ADC data ready
    if ((SSP1STAT & 0x01)) {             // Buffer full
        measure = SSP1BUF;               // Also clears BF bit
        adc_byte_flag = 1;
        if (byte_count++ <= 3) {          // if not full 32 bits
            measure1 |= measure;
            measure1 = measure1 << 8;       // xfer to avg_read pile
            SSP1BUF = LOW;                // Start download again?
        }
        else {
            new_reading_flag = TRUE;        // Flag new reading to be read before next conversion end
            byte_count = 0;                       // Init count
            instant_read = measure1;
            measure1 = 0UL;                     // Set to zero
            adc_byte_flag = 0;
            SSP1IF = FALSE;                      // Clear flag
            SSP1IE = TRUE;                       // Reenable interrupt
            (Start a new ADC conversion via a port bit)
        }
    }
}

in the program the adc_byte_flag is used in program to start the SPI master operation via:

Code: Select all
        if (test_busy() == NO && adc_byte_flag == 0)    // wait next ADC conversion completed and not in the process of reading it already
            SSP1BUF = LOW;                                         // Starts read if conversion complete


The timer interrupt operates fine. The SSP1STAT answers the interrupt but SCLK continues to pour out of the SCLK (in 8 bit groups) as if the SDO were being written to in a continuous fashion or as if the SSP1STAT.BF were not being cleared when the SSPBUF was read. Since the BF is a read-only it cannot be manually cleared.

Has anyone had any experience that might help me?

Side Note: the forum removes the spaces making the program easier to read.
Last edited by SLTom992 on Tue Jun 24, 2014 1:39 am, edited 3 times in total.
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Re: SSP in Master Mode (Intterrupt Problems)

Postby jtemples » Mon Jun 23, 2014 6:41 pm

There's usually no need to add the complication of interrupts to a small SPI read operation. When your conversion is ready, just read the four bytes in a busy-wait loop in your main code. It will be much simpler and probably use fewer CPU cycles than servicing an interrupt.
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Re: SSP in Master Mode (Intterrupt Problems)

Postby SLTom992 » Mon Jun 23, 2014 7:19 pm

As you can see by the interrupt procedure, I have some rapid clocks occurring which are triggering some rather long procedure calls in the main body of the program. Also we need to be able to run the ADC at the highest possible speed which means servicing it as rapidly as possible.
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Re: SSP in Master Mode (Interrupt Problems)

Postby ric » Mon Jun 23, 2014 11:29 pm

SLTom992 wrote:...
Side Note: the forum removes the spaces making the program easier to read.

The spaces are preserved if you put "code" tags around your code. I have just added them for you.

Are you using CCP3 in your program? If it is available, you could use it in "Special Event Trigger" mode to automatically reset Timer3 for you, simplifying your timer rollover ISR code.
Latest test project, an LED matrix display made from one reel of addressable LEDs. here
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Re: SSP in Master Mode (Interrupt Problems)

Postby SLTom992 » Tue Jun 24, 2014 1:34 am

ric - Thanks for that piece of information.

Yes all of the CCP's are used to generate signals of various frequencies depending on what is happening.
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Re: SSP in Master Mode (Interrupt Problems)

Postby jtemples » Tue Jun 24, 2014 2:05 am

I'm not clear on how your code is structured. You're testing a bit in SSPSTAT without that test being qualified by a particular interrupt, which is unusual (also, please use SSPSTATbits.XXX so the person reading your code doesn't have to go to the data sheet to see what you're doing). You're setting SSPIE but not testing SSPIF. You say your goal is to service the SSP as fast as possible, but I don't see that either (e.g., there are lots of instruction cycles between reading SSPBUF and writing SSPBUF). What is the purpose of the 250 uS interrupt?
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Re: SSP in Master Mode (Interrupt Problems)

Postby SLTom992 » Tue Jun 24, 2014 4:30 am

You're quite right that while cleaning up the code I did forget to re-enable the interrupt in the loop.

Doesn't the SSP1IF trigger the interrupt? If the SSP1IF doesn't trigger the interrupt and you don't test SSP1STATbits.BF to see which interrupt went off what do you do?

Reinserting the:

Code: Select all
     // Test for ADC data ready
    if (SSP1STATbits.BF) {             // Buffer full
        measure = SSP1BUF;               // Also clears BF bit
        adc_byte_flag = 1;
        if (byte_count++ <= 3) {          // if not full 32 bits
            measure1 |= measure;
            measure1 = measure1 << 8;       // xfer to avg_read pile
            SSP1BUF = LOW;                // Start download again?
           SSP1IF = FALSE;                 // Clear flag
            SSP1IE = TRUE;                  // Reenable interrupt
       }
    }


Doesn't make any difference to the SSP1SCLK numbers or when they occur. They are not occurring only during the off-time of the ADC but all the time. And I don't reinitialize the ADC until the end of the four byte read.

PS; I was unaware of using the REGISTERbits.bitname protocol since it doesn't seem to be mentioned in the X-8 manual I have. That makes it a lot easier since I was trying to use REGISTER.BITNAME and it wouldn't work on some registers.
Last edited by SLTom992 on Tue Jun 24, 2014 4:39 am, edited 1 time in total.
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Re: SSP in Master Mode (Interrupt Problems)

Postby jtemples » Tue Jun 24, 2014 4:36 am

SSPIF triggers the interrupt, so you check for SSPIF in the interrupt handler. There is no need to look at BF.
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Re: SSP in Master Mode (Interrupt Problems)

Postby SLTom992 » Tue Jun 24, 2014 4:41 am

I have two different high priority interrupts going off so I have to distinguish between them and do so by looking at BF. Of course I could look at the flag as well - does that make a difference?

In an effort to comply with your suggestions I changed the test to the SSP1IF and there was no change.

Also you asked about the timer interrupt. I have a lot of diagnostic lights on the initial production run of the device that have to blink at varying rates to mean different things.
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Re: SSP in Master Mode (Interrupt Problems)

Postby jtemples » Tue Jun 24, 2014 5:42 am

SLTom992 wrote:I have two different high priority interrupts going off so I have to distinguish between them and do so by looking at BF. Of course I could look at the flag as well - does that make a difference?

I can't think of any reason that it wouldn't work, but as I mentioned above, it's unusual, and I can't think of any reason you would need to refer to BF instead of SSPIF. ISRs normally inspect interrupt flags, and BF is not an interrupt flag.

In an effort to comply with your suggestions I changed the test to the SSP1IF and there was no change.

Can you create a minimal, single file application that demonstrates the problem?

Also you asked about the timer interrupt. I have a lot of diagnostic lights on the initial production run of the device that have to blink at varying rates to mean different things.


You have a 4 kHz interrupt to blink LEDs? Is your PIC really running at 4 MHz as implied in one of your comments above? If so, that interrupt is consuming about 10% of your CPU cycles. Ric already asked about CCPs; is one of TMR2/4/6 available to give you a periodic interrupt?
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