GIE not set

(instructions, reset, WDT, specifications...) PIC17Cxx, PIC18Fxxx

GIE not set

Postby bdrmachine » Tue Jan 05, 2016 2:09 am

I wrote a quick MPLABX XC8 project to debug my original 18F4620 program. For some reason the interrupt control bits do not get set up. GIE and PEIE never get changed in the watch window even while single stepping through the code. Could some one please tell me why this code doesn't work?

Thanks Much for this and all the insight this forum has given me!
Brian




#define _XTAL_FREQ 20000000


// CONFIG1H
#pragma config OSC = HS // Oscillator Selection bits (HS oscillator)
#pragma config FCMEN = OFF // Fail-Safe Clock Monitor Enable bit (Fail-Safe Clock Monitor disabled)
#pragma config IESO = OFF // Internal/External Oscillator Switchover bit (Oscillator Switchover mode disabled)

// CONFIG2L
#pragma config PWRT = OFF // Power-up Timer Enable bit (PWRT disabled)
#pragma config BOREN = SBORDIS // Brown-out Reset Enable bits (Brown-out Reset enabled in hardware only (SBOREN is disabled))
#pragma config BORV = 3 // Brown Out Reset Voltage bits (Minimum setting)

// CONFIG2H
#pragma config WDT = OFF // Watchdog Timer Enable bit (WDT disabled (control is placed on the SWDTEN bit))
#pragma config WDTPS = 32768 // Watchdog Timer Postscale Select bits (1:32768)

// CONFIG3H
#pragma config CCP2MX = PORTC // CCP2 MUX bit (CCP2 input/output is multiplexed with RC1)
#pragma config PBADEN = OFF // PORTB A/D Enable bit (PORTB<4:0> pins are configured as digital I/O on Reset)
#pragma config LPT1OSC = OFF // Low-Power Timer1 Oscillator Enable bit (Timer1 configured for higher power operation)
#pragma config MCLRE = ON // MCLR Pin Enable bit (MCLR pin enabled; RE3 input pin disabled)

// CONFIG4L
#pragma config STVREN = OFF // Stack Full/Underflow Reset Enable bit (Stack full/underflow will not cause Reset)
#pragma config LVP = OFF // Single-Supply ICSP Enable bit (Single-Supply ICSP Disabled)
#pragma config XINST = OFF // Extended Instruction Set Enable bit (Instruction set extension and Indexed Addressing mode disabled (Legacy mode))

// CONFIG5L
#pragma config CP0 = OFF // Code Protection bit (Block 0 (000800-003FFFh) not code-protected)
#pragma config CP1 = OFF // Code Protection bit (Block 1 (004000-007FFFh) not code-protected)
#pragma config CP2 = OFF // Code Protection bit (Block 2 (008000-00BFFFh) not code-protected)
#pragma config CP3 = OFF // Code Protection bit (Block 3 (00C000-00FFFFh) not code-protected)

// CONFIG5H
#pragma config CPB = OFF // Boot Block Code Protection bit (Boot block (000000-0007FFh) not code-protected)
#pragma config CPD = OFF // Data EEPROM Code Protection bit (Data EEPROM not code-protected)

// CONFIG6L
#pragma config WRT0 = OFF // Write Protection bit (Block 0 (000800-003FFFh) not write-protected)
#pragma config WRT1 = OFF // Write Protection bit (Block 1 (004000-007FFFh) not write-protected)
#pragma config WRT2 = OFF // Write Protection bit (Block 2 (008000-00BFFFh) not write-protected)
#pragma config WRT3 = OFF // Write Protection bit (Block 3 (00C000-00FFFFh) not write-protected)

// CONFIG6H
#pragma config WRTC = OFF // Configuration Register Write Protection bit (Configuration registers (300000-3000FFh) not write-protected)
#pragma config WRTB = OFF // Boot Block Write Protection bit (Boot Block (000000-0007FFh) not write-protected)
#pragma config WRTD = OFF // Data EEPROM Write Protection bit (Data EEPROM not write-protected)

// CONFIG7L
#pragma config EBTR0 = OFF // Table Read Protection bit (Block 0 (000800-003FFFh) not protected from table reads executed in other blocks)
#pragma config EBTR1 = OFF // Table Read Protection bit (Block 1 (004000-007FFFh) not protected from table reads executed in other blocks)
#pragma config EBTR2 = OFF // Table Read Protection bit (Block 2 (008000-00BFFFh) not protected from table reads executed in other blocks)
#pragma config EBTR3 = OFF // Table Read Protection bit (Block 3 (00C000-00FFFFh) not protected from table reads executed in other blocks)

// CONFIG7H
#pragma config EBTRB = OFF // Boot Block Table Read Protection bit (Boot Block (000000-0007FFh) not protected from table reads executed in other blocks)


//#include "lcd.h";
//#include "USART.h";
#include <xc.h>;

void delay_ms(unsigned char delaytime);

unsigned char count=0;
unsigned char rx_dat=0;
unsigned char rx_file[128];




void main(void) {

unsigned int a;


IPEN = 0; //Interrupt Priority disabled
PEIE = 1; //Peripheral interrupt enabled
GIE =1; //Global interrupt enabled

ADON = 0; //A/D converter disabled
TRISA = 0;

while (1)
{
RA0=0;
//delay_ms(200);
RA0=1;
}
return;
}

void delay_ms(unsigned char delaytime)
{
do
{
__delay_ms(1);
}
while (--delaytime);
}
bdrmachine
 
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Re: GIE not set

Postby AussieSusan » Tue Jan 05, 2016 2:58 am

It might be a fault with the watch window operation. Have you tried to examine the register, but not through the watch window, when you have stepped to just after the code line where you set the bit(s)?
Susan
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Re: GIE not set

Postby bdrmachine » Tue Jan 05, 2016 3:42 am

I looked at the variables window, the results are the same.
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Re: GIE not set

Postby bdrmachine » Tue Jan 05, 2016 3:51 am

I'm using MPLABX 3.15 on a linux (Ubuntu 15.05 ) system if that helps any.
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Re: GIE not set

Postby bdrmachine » Wed Jan 06, 2016 1:39 am

Oh I forgot one other detail. I'm using a MPLAB Real ICE debugger.
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Re: GIE not set

Postby ric » Wed Jan 06, 2016 2:19 am

I would agree with Susan, that this is probably an artifact of how the debugger works.
Try copying the INTCON register into another variable, and then watch that variable to see if GIE (bit 7) and PEIE (bit 6) get set.
Latest test project, an LED matrix display made from one reel of addressable LEDs. here
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Re: GIE not set

Postby jtemples » Fri Jan 08, 2016 8:09 pm

You haven't said if your code works as expected or not.

I had reported a bug in the handling of GIE in MPLAB X when using a hardware debugger (it was always 0) but I don't know if it was ever fixed.
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